This invention relates generally to matched filters, as well as to spread spectrum, code division, multiple access (CDMA) receivers and, more particularly, to matched filters for correlating a spreading code, such as a pseudonoise (PN) spreading code, with sampled received data.
The matched filter is known to be a relatively simple yet powerful and versatile device. For these reasons it has been utilized for impulse response measurements and for making an initial synchronization to a received data stream. One specific application includes CDMA receivers. Other potential applications include newer, so-called third generation (3G), wide-band CDMA receivers. The hardware implementations of such matched filters typically employ a number of gates that are interconnected into flip-flops (FFs), and which are located within an Application Specific Integrated Circuit (ASIC).
For advanced applications, such as the 3G CDMA application, the complexity of the matched filter is increased, as is the filter length (e.g., 128 or 256 taps with an oversampling ratio of up to four.) This increase in complexity requires a large number of gates. One result of the large number of required gates, combined with the typically high clocking frequency (e.g., 16 MHz or 20 MHz), is an increase in ASIC power consumption. This is due to the large number of gate state changes that can occur on each clock transition. As is well known, the most power is consumed when gates change state or switch from one state to another (high to low or low to high). As such, the more gates that change state per unit time, the greater is the power consumption. For portable and battery powered devices, such as radiotelephones and personal communicators, the increased power consumption has a direct impact on xe2x80x98talk timexe2x80x99 and xe2x80x98standby timexe2x80x99, i.e., the time available for communications before the battery needs to be recharged. The increased power consumption can also have ramifications in the overall design and layout of the circuitry.
A conventional matched filter may be considered to have a basically linear (logically) architecture. In the conventional matched filter a reference code (one bit wide) is held in one location and the incoming data, which is typically more than one bit wide, is moved through (down) the filter, filter stage by filter stage. This results in numerous logic state changes in the ASIC gates. By example, in a CDMA code acquisition application the reference code will typically be one bit wide, but have a length of, for example, 128 bits or 256 bits.
Referring to FIG. 1, in the conventional matched filter 1 the tap coefficients are loaded into tap registers 2, and are remain fixed in position as data passes through a multi-stage delay line 3. In this example the data words are input Inphase (IIN) and Quadrature (QIN) words, and are typically comprised of a plurality of bits. The outputs of the flip-flop (FF) registers 3A (each typically several bits wide) of the delay line 3, as well as the outputs of the tap coefficient registers 2, are input to multipliers 4. When complex spreading is used, the effect is to multiply IIN by both the I and Q tap coefficients, and to multiply QIN by both the I and Q tap coefficients. As pairs of IIN and QIN values propagate down the delay line 3 under the control of a clock (CLK) signal 3B, new IIN and QIN values are loaded into the input stage. Assuming that the input data stream matches (is correlated with) the I and Q coefficients held in the registers 2, e.g., I and Q coefficients that represent a PN (de)spreading code, at some point a maximum output (correlation peak) will be observed from the outputs Isum and Qsum of an adder tree structure (shown generally as summation nodes Isum 5A and Qsum 5B.)
In other embodiments, such as one using real code spreading (as opposed to complex code spreading), differences exist in the multiplier/adder tree structure. However, the basic delay line structure remains the same as the complex code spreading embodiment.
While being relatively straightforward to implement, the conventional matched filter 1 exhibits many state changes in the outputs of the delay line flip-flops (FF). If one assumes that the I and Q delay lines 3A and 3B are both three bits wide, and up to 1024 FFs long (256 taps*4 times oversampling), then (3*1024*2=6,144) FFs are loaded on each clock cycle. If the probability that a FF changes state when loaded is P(Ffchange)=0.5, then on average 3,072 state changes occur on every clock cycle. Each state change causes the ASIC containing the matched filter delay line 3 to consume power.
According to reasonable estimates, the matched filter for a 3G CDMA embodiment (assuming four times oversampling and 256 taps) would be the greatest single power consumer in the digital ASIC. It is thus desirable to reduce the power consumption of the matched filter(s) in the 3G CDMA application, as well as in other applications where matched filters may be employed.
It is a first object and advantage of this invention to provide an improved matched filter that exhibits a reduced power consumption.
It is a further object and advantage of this invention to provide an improved matched filter having a ring buffer architecture, wherein the received data samples are stored in registers and are not shifted through a delay line, and wherein the coefficient data is shifted relative to the fixed data samples thereby significantly reducing the number of gate logic state changes per clock cycle.
It is another object and advantage of this invention to provide a mobile station that is constructed to include the improved matched filter having the ring buffer architecture that exhibits reduced power consumption.
The foregoing and other problems are overcome and the objects are realized by methods and apparatus in accordance with embodiments of this invention.
A matched filter is disclosed for synchronizing a spreading code with a sampled received data stream in a receiver, such as a mobile station receiver in a spread spectrum, code division wireless communications system. The matched filter is constructed to include a ring buffer architecture wherein received data samples are loaded one sample at a time, such that the oldest (active) sample is replaced by the newest sample, and a spreading code is shifted within the matched filter to a predetermined position in relation to the ring buffer. As such, the matched filter of this invention may be termed a xe2x80x9cring matched filterxe2x80x9d to distinguish it from the conventional linear matched filters, such as the one described above with respect to FIG. 1.
Reference to the oldest (active) sample is made to highlight an embodiment wherein, by example, a 256 tap filter is operated in a 128 tap mode or a 64 tap mode by xe2x80x9chalvingxe2x80x9d or xe2x80x9cquarteringxe2x80x9d the ring buffer through the use of multiplexers. In this case, the xe2x80x9coldestxe2x80x9d sample in the ring buffer may not be overwritten, but, for example, the 128th or 64th sample will be. Thus, and while there may be stored samples in the ring buffer that may have been stored longer than the sample being overwritten, the sample being overwritten is considered herein to be in the xe2x80x9cactivexe2x80x9d portion of the ring buffer, while the older samples are considered herein to be in an xe2x80x9cinactivexe2x80x9d portion of the ring buffer (e.g., in stages between 129-256 for the 128 tap mode case.)
One significant advantage of the ring matched filter according to the invention is that it consumes less power than the conventional (linear) matched filter discussed above, wherein the reference code (typically one bit) is held still and the incoming multi-bit data is shifted through the filter""s delay line. This conventional approach results in more ASIC logic state changes as compared to the ring matched filter of this invention, wherein the incoming data samples are held still and only the one bit spreading code is moved.
Also disclosed is a mobile station for receiving a spread spectrum, code division transmission from at least one transmitter such as, but not limited to, a base station. The mobile station contains a receiver for outputting data samples, and further contains a multi-tap ring matched filter. The ring matched filter is constructed to have first circuitry for storing an individual one of a received data sample into an individual one of a plurality storage registers such that an active data sample that has been stored for the longest period of time is overwritten with a most recently received data sample. The ring matched filter is further constructed to have second circuitry for serially shifting coefficient bits of at least one multi-bit spreading code relative to the storage registers for sequentially and simultaneously correlating the at least one multi-bit spreading code with all of the stored data samples, for a case with no oversampling, while significantly reducing power consumption by limiting state changes of flip-flops. For a case with higher oversampling, for example two times oversampling, one set of corresponding data samples (e.g. odd samples) are correlated at one instant (clock cycle), while at another clock cycle another set of corresponding data samples (e.g. even samples) are correlated.